I attended the IEEE Hot Chips Conference at Stanford and I wanted to share some of the interesting developments related to digital storage and memory technologies and other interesting developments. These include several talks that showed UCIe chiplet interconnect implementations, SRAM and DRAM improvements from Marvell and Rapidus’s success with their 2nm semiconductor fab.
The open chiplet interconnect standard, UCIe was implemented on several chips that were showing at Hot Chips. Here are a few examples. The image below is a slide from a AyarLabs optical I/O chiplet.
At a Korean-based AI company, Rebellions’ exhibit at Hot Chips they were showing a UCIe-based AI chiplet as shown below.
Lightmatter spoke about a 3D interposer which enables an ASIC built with UCIe IP and laser communication as shown in the image below.
Celestial AI was showing an SoC combining in-die optical I/O with electrical interconnects, including UCIe as shown below.
UC Berkeley has been training students on taping out class chips using Chipyard as part of their education, resulting in real chip results. Students report that this is one of their most intense and fun classes at the University and it attracts more than just engineering students. As the slide below shows UCIe and other open source technologies are used in making these chips.
Mark Kuemerle, VP of Technology at Marvell gave a talk on what they called a revolution in memory architecture for the data center. In particular the Marvell talk focused on a method for increasing the capacity and bandwidth of static random-access memory, SRAM. Marvell has a 2nm SRAM platform manufactured at TSMC.
The company has made innovations in write assist, stability assist, pioneering high-sigma design modeling to capture tail bits and row plus column redundancy to enable low voltages and high overall yields. As a consequence Marvell’s custom SRAM achieves significant advantages over HBM and other embedded IP memory as shown below.
Marvell said they achieve this by running faster and with more ports. The company also discussed its custom HBM architectures using IO chiplets with the companies D2D chiplet interconnect. The company announced at Hot Chips a 65 Gbps/wire Bi-Directional Die-to-Die interface IP in 2nm for the next generation of XPUs. They also showed their Structura A and X high capacity memories for near memory accelerators and memory expansion.
Rapidus had a keynote talk on the last day where Rapidus CEO Atsuyoshi Kolke spoke about the building and initial operation of the company’s 2nm semiconductor fab on the Island of Hokkaido in Japan. In April the company had their first EUV test, shown below.
Hot Chips showed UCIe chiplet interconnects, Marvell’s custom SRAM and HBM developments and Rapidus details on their 2nm semiconductor fab.